Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A processor cache is a cache that can be used by a processor such as the central processing unit (CPU) of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations. As long as most memory accesses are cached memory locations, the average latency of memory accesses are closer to the cache latency than to the latency of main memory. When the processor needs to read from or write to a location in main memory, the processor first checks whether a copy of that data is in the cache. If so, the processor immediately reads from or writes to the cache, which is typically much faster than reading from or writing to main memory.
Most modern desktop and server processors have at least three independent caches: an instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, and a translation look-aside buffer (TLB) used to speed up virtual-to-physical address translation for both executable instructions and data. Data cache is usually organized as a hierarchy of more cache levels (L1, L2, etc.). Multi-level caches generally operate by checking the smallest Level 1 (L1) cache first; if L1 is hit, the processor proceeds at high speed. If the smaller cache misses, the next larger cache (L2) is checked, and so on, before external memory is checked.
Ionizing radiation induced single-event upsets (SEUs), also known as soft errors, in semiconductor memories have been recognized for a long time as a major reliability issue in electronic systems. Due to their large share of the transistor budget and die area, on-chip caches suffer from a significantly higher soft-error rate (SER) than other on-chip components at the current and near future technologies.
The present disclosure appreciates that reliability of the data array in on-chip caches is further emphasized due to importance of the correctness of cache accesses. An incorrect cache access (i.e., data/instruction read out from wrong cache lines or data written into wrong cache lines) may crash the subsequent computation/communication, external memory, or storage systems, leading to an overall system failure or program inaccuracy. On the other hand, any practical reliable design is subject to various stringent performance, area, and energy constraints.